[all-commits] [llvm/llvm-project] 6b429a: [RISCV] Improve RV64 codegen for i32 ISD::SADDO wh...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 6b429a9cf93342a280d67f63104285888c9884d1
      https://github.com/llvm/llvm-project/commit/6b429a9cf93342a280d67f63104285888c9884d1
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-05-08 (Mon, 08 May 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/xaluo.ll

  Log Message:
  -----------
  [RISCV] Improve RV64 codegen for i32 ISD::SADDO when RHS is constant.

This uses the same sequence we get from LegalizeDAG for i32 on RV32, but modified
to use W instructions.

When the RHS is constant one of the setccs simplifies to a constant and the xor will either
be an xori with 1 or get removed.

When the RHS is not a constant it was not an obvious improvement and it was a regression
when used with a branch. So I've restricted to the constant case.

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D150135