[all-commits] [llvm/llvm-project] 91cff8: [mlir][mem2reg] Expose algorithm internals.

[Théo Degioanni via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 91cff8a71872cf49f0c5c9e5510f8065bfefa3c3
      https://github.com/llvm/llvm-project/commit/91cff8a71872cf49f0c5c9e5510f8065bfefa3c3
  Author: Théo Degioanni <theo.degioanni at nextsilicon.com>
  Date:   2023-05-08 (Mon, 08 May 2023)

  Changed paths:
    M mlir/include/mlir/Dialect/LLVMIR/LLVMIntrinsicOps.td
    M mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td
    M mlir/include/mlir/Dialect/MemRef/IR/MemRef.h
    M mlir/include/mlir/Dialect/MemRef/IR/MemRefOps.td
    M mlir/include/mlir/Interfaces/CMakeLists.txt
    R mlir/include/mlir/Interfaces/Mem2RegInterfaces.h
    R mlir/include/mlir/Interfaces/Mem2RegInterfaces.td
    A mlir/include/mlir/Interfaces/MemorySlotInterfaces.h
    A mlir/include/mlir/Interfaces/MemorySlotInterfaces.td
    M mlir/include/mlir/Transforms/Mem2Reg.h
    M mlir/lib/Dialect/LLVMIR/CMakeLists.txt
    R mlir/lib/Dialect/LLVMIR/IR/LLVMMem2Reg.cpp
    A mlir/lib/Dialect/LLVMIR/IR/LLVMMemorySlot.cpp
    M mlir/lib/Dialect/MemRef/IR/MemRefMem2Reg.cpp
    M mlir/lib/Interfaces/CMakeLists.txt
    R mlir/lib/Interfaces/Mem2RegInterfaces.cpp
    A mlir/lib/Interfaces/MemorySlotInterfaces.cpp
    M mlir/lib/Transforms/CMakeLists.txt
    M mlir/lib/Transforms/Mem2Reg.cpp

  Log Message:
  -----------
  [mlir][mem2reg] Expose algorithm internals.

This patch refactors the Mem2Reg infrastructure. It decouples
analysis from promotion, allowing for more control over the execution of
the logic. It also adjusts the interfaces to be less coupled to mem2reg
and more general. This will be useful for an upcoming revision
introducing generic SROA.

Reviewed By: gysit

Differential Revision: https://reviews.llvm.org/D149825