[all-commits] [llvm/llvm-project] f9fa8a: [RISCV] Add scheduling information for Zba and Zbb...

[Michael Maitland via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: f9fa8a59970451ffd9ffc6b4c0554c7e7bd25ab0
      https://github.com/llvm/llvm-project/commit/f9fa8a59970451ffd9ffc6b4c0554c7e7bd25ab0
  Author: Michael Maitland <michaeltmaitland at gmail.com>
  Date:   2023-05-05 (Fri, 05 May 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVSchedSiFive7.td

  Log Message:
  -----------
  [RISCV] Add scheduling information for Zba and Zbb to RISCVSchedSiFive7.td

Based on the following description from Andrew W.

Instructions not mentioned here behave the same as integer ALU ops
rev8 only executes in the late-A and late-B ALUs
shNadd[.uw] only execute on the early-B and late-B ALUs
clz[w], ctz[w], and orc.b and all rotates only execute in the late-B ALU
pcnt[w] looks exactly like integer multiply
This patch does not account for early/late ALU in the model. It is coded based
on the pipes only.

Co-Authored-By: topperc <craig.topper at sifive.com>

Differential Revision: https://reviews.llvm.org/D149497