[all-commits] [llvm/llvm-project] 7b3b17: [RISCV] Add DecoderNamespace to Zcmt instructions.

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 7b3b178c825bfcf196685311bf33e4a5fa8ca8aa
      https://github.com/llvm/llvm-project/commit/7b3b178c825bfcf196685311bf33e4a5fa8ca8aa
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-05-05 (Fri, 05 May 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfoZc.td

  Log Message:
  -----------
  [RISCV] Add DecoderNamespace to Zcmt instructions.

The Zcmt instructions overlap encoding space with some C extension
instructions. Isolate to a separate namespace.

Reviewed By: VincentWu

Differential Revision: https://reviews.llvm.org/D149891


  Commit: 913b95fb80853894c479753f4f03a5efd3b0a5c8
      https://github.com/llvm/llvm-project/commit/913b95fb80853894c479753f4f03a5efd3b0a5c8
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-05-05 (Fri, 05 May 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoZc.td

  Log Message:
  -----------
  [RISCV] Add X1 as implicit def of cm.jalt.

This instruction updates the RA register.

Reviewed By: VincentWu

Differential Revision: https://reviews.llvm.org/D149933


Compare: https://github.com/llvm/llvm-project/compare/f9dba933c6de...913b95fb8085