[all-commits] [llvm/llvm-project] 6e7ca6: Revert "[RISCV] Add sifive-x280 processor with all...

[Michael Maitland via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 6e7ca6839def260e57334040a586934011f0098d
      https://github.com/llvm/llvm-project/commit/6e7ca6839def260e57334040a586934011f0098d
  Author: Michael Maitland <michaeltmaitland at gmail.com>
  Date:   2023-05-05 (Fri, 05 May 2023)

  Changed paths:
    M clang/test/Driver/riscv-cpus.c
    M clang/test/Misc/target-invalid-cpu-note.c
    M llvm/docs/ReleaseNotes.rst
    M llvm/lib/Target/RISCV/RISCVProcessors.td

  Log Message:
  -----------
  Revert "[RISCV] Add sifive-x280 processor with all of its extensions"

Test still not working...

This reverts commit a11dfd0fe6b1c38495f7de9858a2d1839d2902b9.