[all-commits] [llvm/llvm-project] a11dfd: [RISCV] Add sifive-x280 processor with all of its ...

[Michael Maitland via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: a11dfd0fe6b1c38495f7de9858a2d1839d2902b9
      https://github.com/llvm/llvm-project/commit/a11dfd0fe6b1c38495f7de9858a2d1839d2902b9
  Author: Michael Maitland <michaeltmaitland at gmail.com>
  Date:   2023-05-05 (Fri, 05 May 2023)

  Changed paths:
    M clang/test/Driver/riscv-cpus.c
    M clang/test/Misc/target-invalid-cpu-note.c
    M llvm/docs/ReleaseNotes.rst
    M llvm/lib/Target/RISCV/RISCVProcessors.td

  Log Message:
  -----------
  [RISCV] Add sifive-x280 processor with all of its extensions

Add sifive-x280 processor that uses the SiFive7 scheduler model.

Differential Revision: https://reviews.llvm.org/D149710