[all-commits] [llvm/llvm-project] 55e196: [RISCV] Add sifive-x280 processor with all of its ...

[Michael Maitland via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 55e196e7718c543b4492f2949c13de003a4ba443
      https://github.com/llvm/llvm-project/commit/55e196e7718c543b4492f2949c13de003a4ba443
  Author: Michael Maitland <michaeltmaitland at gmail.com>
  Date:   2023-05-05 (Fri, 05 May 2023)

  Changed paths:
    M clang/test/Driver/riscv-cpus.c
    M llvm/docs/ReleaseNotes.rst
    M llvm/lib/Target/RISCV/RISCVProcessors.td

  Log Message:
  -----------
  [RISCV] Add sifive-x280 processor with all of its extensions

Add sifive-x280 processor that uses the SiFive7 scheduler model.

Differential Revision: https://reviews.llvm.org/D149710


  Commit: cd02b69e75dd677acdc6c77e6b7bb8d02099b7c0
      https://github.com/llvm/llvm-project/commit/cd02b69e75dd677acdc6c77e6b7bb8d02099b7c0
  Author: Michael Maitland <michaeltmaitland at gmail.com>
  Date:   2023-05-05 (Fri, 05 May 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVSchedSiFive7.td

  Log Message:
  -----------
  [RISCV] Add scheduling information for Zba and Zbb to RISCVSchedSiFive7.td

Based on the following description from Andrew W.

- Instructions not mentioned here behave the same as integer ALU ops
- rev8 only executes in the late-A and late-B ALUs
- shNadd[.uw] only execute on the early-B and late-B ALUs
- clz[w], ctz[w], and orc.b and all rotates only execute in the late-B ALU
- pcnt[w] looks exactly like integer multiply

This patch does not account for early/late ALU in the model. It is coded based
on the pipes only.

Differential Revision: https://reviews.llvm.org/D149497

Co-Authored-By: topperc <craig.topper at sifive.com>


  Commit: b77d6f51ba4e330cd3f185720cedee1ff5fcb03e
      https://github.com/llvm/llvm-project/commit/b77d6f51ba4e330cd3f185720cedee1ff5fcb03e
  Author: Michael Maitland <michaeltmaitland at gmail.com>
  Date:   2023-05-05 (Fri, 05 May 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVSchedSiFive7.td

  Log Message:
  -----------
  [RISCV] Add Scheduling information for Zfh to SiFive7 model

Everything is the same as F extension, except sqrt and div are 13
cycles faster.

Differential Revision: https://reviews.llvm.org/D149498


Compare: https://github.com/llvm/llvm-project/compare/30af2fb33ed2...b77d6f51ba4e