[all-commits] [llvm/llvm-project] d9683a: [RISCV] Fix extract_vector_elt on i1 at idx 0 bein...

[Luke Lau via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: d9683a70fef48cfaee2c83147a3b26f4f90162a2
      https://github.com/llvm/llvm-project/commit/d9683a70fef48cfaee2c83147a3b26f4f90162a2
  Author: Luke Lau <luke at igalia.com>
  Date:   2023-05-04 (Thu, 04 May 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rvv/constant-folding-crash.ll
    M llvm/test/CodeGen/RISCV/rvv/extractelt-i1.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vector-shuffle-reverse.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-i1.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-store.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vreductions-mask.ll
    M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll
    M llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll

  Log Message:
  -----------
  [RISCV] Fix extract_vector_elt on i1 at idx 0 being inverted

It looks like the intention here is to truncate a XLenVT -> i1, in
which case we should be emitting snez instead of sneq if I'm understanding
correctly.

Reviewed By: jacquesguan, frasercrmck

Differential Revision: https://reviews.llvm.org/D149732