[all-commits] [llvm/llvm-project] cf7607: [AMDGPU][GlobalISel] Check exact width in get*Clas...

[Mateja Marjanovic via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: cf76074a366b3727a1aa8946da6c520130de39be
      https://github.com/llvm/llvm-project/commit/cf76074a366b3727a1aa8946da6c520130de39be
  Author: Mateja Marjanovic <mailto:mmarjano at amd.com>
  Date:   2023-05-03 (Wed, 03 May 2023)

  Changed paths:
    M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
    M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
    M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
    M llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll

  Log Message:
  -----------
  [AMDGPU][GlobalISel] Check exact width in get*ClassForBitWidth and widen if necessary

Instead of checking if the given bitwidth is less or equal to a bitwidth of an existing RegClass,
check if it has the exact same value.

For LLVM vector types that don't have a corresponding Register Class, widen them during legalization.
That goes for G_EXTRACT_VECTOR_ELT, G_INSERT_VECTOR_ELT and G_BUILD_VECTOR.

Differential revision: https://reviews.llvm.org/D148096
Reviewers: foad, arsenm