[all-commits] [llvm/llvm-project] f9c1ed: [AMDGPU] Define data layout entries for buffers
Krzysztof Drewniak via All-commits
all-commits at lists.llvm.org
Wed May 3 08:26:13 PDT 2023
Branch: refs/heads/main
Home: https://github.com/llvm/llvm-project
Commit: f9c1ede2543b37fabe9f2d8f8fed5073c475d850
https://github.com/llvm/llvm-project/commit/f9c1ede2543b37fabe9f2d8f8fed5073c475d850
Author: Krzysztof Drewniak <Krzysztof.Drewniak at amd.com>
Date: 2023-05-03 (Wed, 03 May 2023)
Changed paths:
M clang/lib/Basic/Targets/AMDGPU.cpp
M clang/test/CodeGen/target-data.c
M clang/test/CodeGenOpenCL/amdgpu-env-amdgcn.cl
M llvm/docs/AMDGPUUsage.rst
M llvm/lib/IR/AutoUpgrade.cpp
M llvm/lib/Target/AMDGPU/AMDGPU.h
M llvm/lib/Target/AMDGPU/AMDGPUAliasAnalysis.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.f32-no-rtn.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.f32-rtn.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.f64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.v2f16-no-rtn.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.v2f16-rtn.ll
R llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-non-integral-address-spaces.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.atomic.dim.a16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.dim.a16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.load.2d.d16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.load.2d.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.load.2darraymsaa.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.load.3d.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.sample.a16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.sample.d.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.sample.g16.a16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.sample.g16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.store.2d.d16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.atomic.dim.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.add.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.cmpswap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.fadd-with-ret.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.fadd.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.format.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.format.f32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.load.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.i8.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.add.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.cmpswap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.fadd-with-ret.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.fadd.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.format.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.store.format.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.store.format.f32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.tbuffer.load.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.tbuffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.image.load.1d.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.image.sample.1d.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.raw.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/addrspacecast-captured.ll
M llvm/test/CodeGen/AMDGPU/annotate-kernel-features-hsa.ll
M llvm/test/CodeGen/AMDGPU/buffer-atomic-fadd.f32-no-rtn.ll
M llvm/test/CodeGen/AMDGPU/buffer-atomic-fadd.f32-rtn.ll
M llvm/test/CodeGen/AMDGPU/buffer-atomic-fadd.f64.ll
M llvm/test/CodeGen/AMDGPU/buffer-atomic-fadd.v2f16-no-rtn.ll
M llvm/test/CodeGen/AMDGPU/buffer-atomic-fadd.v2f16-rtn.ll
M llvm/test/CodeGen/AMDGPU/buffer-intrinsics-mmo-offsets.ll
M llvm/test/CodeGen/AMDGPU/cgp-addressing-modes.ll
M llvm/test/CodeGen/AMDGPU/extract_subvector_vec4_vec3.ll
M llvm/test/CodeGen/AMDGPU/force-alwaysinline-lds-global-address.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.buffer.load.format.f16.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.buffer.load.format.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.buffer.store.format.f16.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.buffer.store.format.f32.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.buffer.store.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.tbuffer.load.f16.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.tbuffer.load.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.tbuffer.store.f16.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.tbuffer.store.ll
M llvm/test/CodeGen/AMDGPU/legalize-soffset-mbuf.ll
M llvm/test/CodeGen/AMDGPU/loop-idiom.ll
M llvm/test/CodeGen/AMDGPU/mdt-preserving-crash.ll
M llvm/test/CodeGen/AMDGPU/noop-shader-O0.ll
A llvm/test/CodeGen/AMDGPU/nullptr-long-address-spaces.ll
M llvm/test/CodeGen/AMDGPU/nullptr.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-lifetime.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-to-lds-select.ll
M llvm/test/CodeGen/AMDGPU/sgpr-copy-local-cse.ll
M llvm/test/CodeGen/AMDGPU/splitkit-getsubrangeformask.ll
M llvm/test/CodeGen/AMDGPU/unroll.ll
M llvm/test/CodeGen/AMDGPU/unsupported-image-a16.ll
M llvm/test/CodeGen/AMDGPU/unsupported-image-g16.ll
M llvm/test/CodeGen/AMDGPU/vgpr-liverange-ir.ll
M llvm/test/CodeGen/MIR/AMDGPU/custom-pseudo-source-values.ll
M llvm/test/Instrumentation/AddressSanitizer/AMDGPU/adaptive_constant_global_redzones.ll
M llvm/test/Instrumentation/AddressSanitizer/AMDGPU/adaptive_global_redzones.ll
M llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan_do_not_instrument_lds.ll
M llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan_do_not_instrument_scratch.ll
M llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan_instrument_constant_address_space.ll
M llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan_instrument_generic_address_space.ll
M llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan_instrument_global_address_space.ll
M llvm/test/Instrumentation/AddressSanitizer/AMDGPU/global_metadata_addrspacecasts.ll
M llvm/test/Instrumentation/AddressSanitizer/AMDGPU/no_redzones_in_lds_globals.ll
M llvm/test/Instrumentation/AddressSanitizer/AMDGPU/no_redzones_in_scratch_globals.ll
M llvm/test/Transforms/AlignmentFromAssumptions/amdgpu-crash.ll
M llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-i16.ll
M llvm/test/Transforms/EarlyCSE/AMDGPU/memrealtime.ll
M llvm/test/Transforms/IndVarSimplify/AMDGPU/no-widen-to-i64.ll
M llvm/test/Transforms/InferAddressSpaces/AMDGPU/noop-ptrint-pair.ll
M llvm/test/Transforms/InferAddressSpaces/AMDGPU/ptrmask.ll
M llvm/test/Transforms/InferAddressSpaces/X86/noop-ptrint-pair.ll
M llvm/test/Transforms/Inline/AMDGPU/amdgpu-inline-alloca-argument.ll
M llvm/test/Transforms/InstCombine/AMDGPU/memcpy-from-constant.ll
M llvm/test/Transforms/InstCombine/alloca-in-non-alloca-as.ll
M llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/aa-metadata.ll
M llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/adjust-alloca-alignment.ll
M llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/complex-index.ll
M llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/extended-index.ll
M llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/gep-bitcast.ll
M llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/insertion-point.ll
M llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/interleaved-mayalias-store.ll
M llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/invariant-load.ll
M llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/merge-stores-private.ll
M llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/merge-stores.ll
M llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/missing-alignment.ll
M llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/multiple_tails.ll
M llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/no-implicit-float.ll
M llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/optnone.ll
M llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/pointer-elements.ll
M llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/selects-inseltpoison.ll
M llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/selects.ll
M llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/store_with_aliasing_load.ll
M llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/weird-type-accesses.ll
M llvm/test/Transforms/LoopLoadElim/pr46854-adress-spaces.ll
M llvm/test/Transforms/LoopStrengthReduce/AMDGPU/atomics.ll
M llvm/test/Transforms/LoopStrengthReduce/AMDGPU/different-addrspace-addressing-mode-loops.ll
M llvm/test/Transforms/LoopStrengthReduce/AMDGPU/lsr-invalid-ptr-extend.ll
M llvm/test/Transforms/LoopStrengthReduce/AMDGPU/lsr-postinc-pos-addrspace.ll
M llvm/test/Transforms/LoopStrengthReduce/AMDGPU/preserve-addrspace-assert.ll
M llvm/test/Transforms/OpenMP/attributor_pointer_offset_crash.ll
M llvm/test/Transforms/OpenMP/spmdization_constant_prop.ll
M llvm/test/Transforms/OpenMP/values_in_offload_arrays.alloca.ll
M llvm/test/Transforms/SLPVectorizer/AMDGPU/address-space-ptr-sze-gep-index-assert.ll
M llvm/test/Transforms/VectorCombine/AMDGPU/as-transition-inseltpoison.ll
M llvm/test/Transforms/VectorCombine/AMDGPU/as-transition.ll
M llvm/unittests/Bitcode/DataLayoutUpgradeTest.cpp
Log Message:
-----------
[AMDGPU] Define data layout entries for buffers
Per discussion at
https://discourse.llvm.org/t/representing-buffer-descriptors-in-the-amdgpu-target-call-for-suggestions/68798,
we define two new address spaces for AMDGCN targets.
The first is address space 7, a non-integral address space (which was
already in the data layout) that has 160-bit pointers (which are
256-bit aligned) and uses a 32-bit offset. These pointers combine a
128-bit buffer descriptor and a 32-bit offset, and will be usable with
normal LLVM operations (load, store, GEP). However, they will be
rewritten out of existence before code generation.
The second of these is address space 8, the address space for "buffer
resources". These will be used to represent the resource arguments to
buffer instructions, and new buffer intrinsics will be defined that
take them instead of <4 x i32> as resource arguments. ptr
addrspace(8). These pointers are 128-bits long (with the same
alignment). They must not be used as the arguments to getelementptr or
otherwise used in address computations, since they can have
arbitrarily complex inherent addressing semantics that can't be
represented in LLVM. Even though, like their address space 7 cousins,
these pointers have deterministic ptrtoint/inttoptr semantics, they
are defined to be non-integral in order to prevent optimizations that
rely on pointers being a [0, [addr_max]] value from applying to them.
Future work includes:
- Defining new buffer intrinsics that take ptr addrspace(8) resources.
- A late rewrite to turn address space 7 operations into buffer
intrinsics and offset computations.
This commit also updates the "fallback address space" for buffer
intrinsics to the buffer resource, and updates the alias analysis
table.
Depends on D143437
Reviewed By: arsenm
Differential Revision: https://reviews.llvm.org/D145441
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