[all-commits] [llvm/llvm-project] 8e46ac: [AArch64] Add more efficient bitwise vector reduct...

Sp00ph via All-commits all-commits at lists.llvm.org
Wed May 3 07:56:29 PDT 2023

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 8e46ac3623b4dfbd7127fc0deee5cf82a3f9d472
  Author: Sp00ph <markuseverling at gmail.com>
  Date:   2023-05-03 (Wed, 03 May 2023)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/test/CodeGen/AArch64/dag-combine-setcc.ll
    M llvm/test/CodeGen/AArch64/double_reduct.ll
    M llvm/test/CodeGen/AArch64/illegal-floating-point-vector-compares.ll
    M llvm/test/CodeGen/AArch64/reduce-and.ll
    M llvm/test/CodeGen/AArch64/reduce-or.ll
    M llvm/test/CodeGen/AArch64/reduce-xor.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-log-reduce.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-ptest.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ptest.ll
    M llvm/test/CodeGen/AArch64/vecreduce-and-legalization.ll

  Log Message:
  [AArch64] Add more efficient bitwise vector reductions.

Improves the codegen for VECREDUCE_{AND,OR,XOR} operations on AArch64.
Currently, these are fully scalarized, except if the vector is a <N x i1>. This
patch improves the codegen down to O(log(N)) where N is the length of the
vector for vectors whose elements are not i1, by repeatedly applying the
bitwise operations to the two halves of the vector. <N x i1> bitwise reductions
are handled using VECREDUCE_{UMAX,UMIN,ADD} instead.

I had to update quite a few codegen tests with these changes, with a general
downward trend in instruction count. Since the vector reductions already have
tests, I haven't added any new tests myself.

Differential Revision: https://reviews.llvm.org/D148185

More information about the All-commits mailing list