[all-commits] [llvm/llvm-project] 20bf8c: [mlir][SparseTensor][ArmSVE] Disable scalable vect...

Andrzej WarzyƄski via All-commits all-commits at lists.llvm.org
Tue May 2 14:15:18 PDT 2023

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 20bf8c403c5a8db6107358e534fb3ab5dd0ae9a3
  Author: Andrzej Warzynski <andrzej.warzynski at arm.com>
  Date:   2023-05-02 (Tue, 02 May 2023)

  Changed paths:
    M mlir/test/Integration/Dialect/SparseTensor/CPU/concatenate_dim_1.mlir

  Log Message:
  [mlir][SparseTensor][ArmSVE] Disable scalable vectorisation in a test

The MLIR SVE integration tests are now enabled in the
clang-aarch64-full-2stage buildbot under emulation (QEMU) and one of the
sparse integration tests is failing [1]:

  * Integration/Dialect/SparseTensor/CPU/concatenate_dim_1.mlir

That test is failing because we we don't have a LIT substitution to
  ; RUN: mlir-cpu-runner <command>
  ; RUN: <emulator> mlir-cpu-runner <command>
clang-aarch64-full-2stage does not support SVE natively and hence all
SVE integration tests require emulation. Other SVE tests use `lli` (for
which we do have the required substitution) and hence are not affected.

This patch simplifies concatenate_dim_1.mlir to always use fixed-width
vectorisation. We will re-enable scalable vectorisation once LIT
substitutions for `mlir-cpu-runner` are updated.

[1] https://lab.llvm.org/buildbot/#/builders/179/builds/6062

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