[all-commits] [llvm/llvm-project] 41549b: [AArch64] Add sign bits handling for vector compar...

[David Green via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 41549b535097db923386a64ed769bf450943e6a3
      https://github.com/llvm/llvm-project/commit/41549b535097db923386a64ed769bf450943e6a3
  Author: David Green <david.green at arm.com>
  Date:   2023-05-02 (Tue, 02 May 2023)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/lib/Target/AArch64/AArch64ISelLowering.h
    M llvm/test/CodeGen/AArch64/cmp-select-sign.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-masked-gather.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-masked-scatter.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-masked-stores.ll

  Log Message:
  -----------
  [AArch64] Add sign bits handling for vector compare nodes

This adds ComputeNumSignBits for the NEON vector comparison nodes, which all
either return 0 or -1. Also adds sign_extend_inreg from VASHR+VSHL to show it
performing transforms.

Differential Revision: https://reviews.llvm.org/D148624