[all-commits] [llvm/llvm-project] b73229: [SelectionDAG] Use logic right shift to avoid loop...

KanRobert via All-commits all-commits at lists.llvm.org
Mon May 1 21:48:04 PDT 2023

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: b73229e55543b4ba2b293adcb8b7d6025f01f7d9
  Author: Shengchen Kan <shengchen.kan at intel.com>
  Date:   2023-05-02 (Tue, 02 May 2023)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
    A llvm/test/CodeGen/X86/powi-negative-imm.ll

  Log Message:
  [SelectionDAG] Use logic right shift to avoid loop hang

Issue was reported in D149033, `Val` can be negative value and
arithmetic right shift always keeps the sign bit.

BTW, the redundant code `Val = -Val` is removed by this patch.

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