[all-commits] [llvm/llvm-project] 42e79d: [RISCV] Add attribute(riscv_rvv_vector_bits(N)) ba...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 42e79d9771f96110c7f51ee5f39a76517ae44234
      https://github.com/llvm/llvm-project/commit/42e79d9771f96110c7f51ee5f39a76517ae44234
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-04-28 (Fri, 28 Apr 2023)

  Changed paths:
    M clang/docs/ReleaseNotes.rst
    M clang/include/clang/AST/ASTContext.h
    M clang/include/clang/AST/Type.h
    M clang/include/clang/Basic/Attr.td
    M clang/include/clang/Basic/AttrDocs.td
    M clang/include/clang/Basic/DiagnosticSemaKinds.td
    M clang/include/clang/Basic/RISCVVTypes.def
    M clang/include/clang/Driver/Options.td
    M clang/include/clang/Sema/Overload.h
    M clang/include/clang/Sema/Sema.h
    M clang/lib/AST/ASTContext.cpp
    M clang/lib/AST/ItaniumMangle.cpp
    M clang/lib/AST/JSONNodeDumper.cpp
    M clang/lib/AST/TextNodeDumper.cpp
    M clang/lib/AST/Type.cpp
    M clang/lib/AST/TypePrinter.cpp
    M clang/lib/Basic/Targets/RISCV.cpp
    M clang/lib/CodeGen/TargetInfo.cpp
    M clang/lib/Sema/SemaCast.cpp
    M clang/lib/Sema/SemaChecking.cpp
    M clang/lib/Sema/SemaExpr.cpp
    M clang/lib/Sema/SemaExprCXX.cpp
    M clang/lib/Sema/SemaOverload.cpp
    M clang/lib/Sema/SemaType.cpp
    A clang/test/CodeGen/attr-riscv-rvv-vector-bits-bitcast.c
    A clang/test/CodeGen/attr-riscv-rvv-vector-bits-call.c
    A clang/test/CodeGen/attr-riscv-rvv-vector-bits-cast.c
    A clang/test/CodeGen/attr-riscv-rvv-vector-bits-codegen.c
    A clang/test/CodeGen/attr-riscv-rvv-vector-bits-globals.c
    A clang/test/CodeGen/attr-riscv-rvv-vector-bits-types.c
    A clang/test/CodeGen/riscv-rvv-vls-arith-ops.c
    A clang/test/CodeGen/riscv-rvv-vls-bitwise-ops.c
    A clang/test/CodeGen/riscv-rvv-vls-compare-ops.c
    A clang/test/CodeGen/riscv-rvv-vls-shift-ops.c
    A clang/test/CodeGen/riscv-rvv-vls-subscript-ops.c
    A clang/test/CodeGenCXX/riscv-mangle-rvv-fixed-vectors.cpp
    A clang/test/CodeGenCXX/riscv-rvv-fixedtypeinfo.cpp
    M clang/test/Driver/riscv-rvv-vector-bits.c
    M clang/test/Sema/attr-riscv-rvv-vector-bits.c
    A clang/test/Sema/riscv-rvv-explicit-casts-fixed-size.c
    A clang/test/Sema/riscv-rvv-lax-vector-conversions.c
    A clang/test/Sema/riscv-vector-types-support.c
    A clang/test/SemaCXX/attr-riscv-rvv-vector-bits.cpp
    A clang/test/SemaCXX/riscv-rvv-explicit-casts-fixed-size.cpp
    A clang/test/SemaCXX/riscv-rvv-lax-vector-conversions.cpp

  Log Message:
  -----------
  [RISCV] Add attribute(riscv_rvv_vector_bits(N)) based on AArch64 arm_sve_vector_bits.

This allows the user to set the size of the scalable vector so they
can be used in structs and as the type of global variables. This works
by representing the type as a fixed vector instead of a scalable vector
in IR. Conversions to and from scalable vectors are made where necessary
like function arguments/returns and intrinsics.

This features has been requested here
https://github.com/riscv-non-isa/rvv-intrinsic-doc/issues/176
I know arm_sve_vector_bits is used by the Eigen library so this
could be used to port Eigen to RVV.

This patch adds a new preprocessor define `__riscv_v_fixed_vlen` that
is set when -mrvv_vector_bits is passed on the command line.

The code is largely based on the AArch64 code. A lot of code was
copy/pasted and then modiied to RVV. There may be some opportunities
for sharing.

This first patch only supports the LMUL=1 types. Additional changes
will be needed to support other LMULs. I have also not supported
mask vectors.

Differential Revision: https://reviews.llvm.org/D145088