[all-commits] [llvm/llvm-project] d636bc: [RISCV] Introduce unaligned-vector-mem feature

[Philip Reames via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: d636bcb6ae51bf1fe2faff153f3d8f30dc1db8b8
      https://github.com/llvm/llvm-project/commit/d636bcb6ae51bf1fe2faff153f3d8f30dc1db8b8
  Author: Philip Reames <preames at rivosinc.com>
  Date:   2023-04-28 (Fri, 28 Apr 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVFeatures.td
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-load-combine.ll
    M llvm/test/CodeGen/RISCV/rvv/unaligned-loads-stores.ll

  Log Message:
  -----------
  [RISCV] Introduce unaligned-vector-mem feature

This allows us to model and thus test transforms which are legal only when a vector load with less than element alignment are supported. This was originally part of D126085, but was split out as we didn't have a good example of such a transform. As can be seen in the test diffs, we have the recently added concat_vector(loads) -> strided_load transform (from D147713) which now benefits from the unaligned support.

While making this change, I realized that we actually *do* support unaligned vector loads and stores of all types via conversion to i8 element type. For contiguous loads and stores without masking, we actually already implement this in the backend - though we don't tell the optimizer that. For indexed, lowering to i8 requires complicated addressing. For indexed and segmented, we'd have to use indexed. All around, doesn't seem worthwhile pursuing, but makes for an interesting observation.

Differential Revision: https://reviews.llvm.org/D149375