[all-commits] [llvm/llvm-project] bd6fa8: [RISCV] Add tests for illegal fixed length vectors...
Luke Lau via All-commits
all-commits at lists.llvm.org
Fri Apr 28 02:19:27 PDT 2023
Branch: refs/heads/main
Home: https://github.com/llvm/llvm-project
Commit: bd6fa8656af58dc79270cb415ac4aac7ff309159
https://github.com/llvm/llvm-project/commit/bd6fa8656af58dc79270cb415ac4aac7ff309159
Author: Luke Lau <luke at igalia.com>
Date: 2023-04-28 (Fri, 28 Apr 2023)
Changed paths:
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-i2fp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect.ll
Log Message:
-----------
[RISCV] Add tests for illegal fixed length vectors that need widened
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D148518
Commit: 8ead003d8948f1db02bb83d23b177dc545eaf669
https://github.com/llvm/llvm-project/commit/8ead003d8948f1db02bb83d23b177dc545eaf669
Author: Luke Lau <luke at igalia.com>
Date: 2023-04-28 (Fri, 28 Apr 2023)
Changed paths:
M llvm/include/llvm/IR/VPIntrinsics.def
Log Message:
-----------
[VP] Add more functional SD opcodes to definitions
This defines more equivalent base SD opcodes for various VP nodes, so
that getVPForBaseOpcode can do more lookups of VP-equivalent operations.
Reviewed By: frasercrmck
Differential Revision: https://reviews.llvm.org/D148520
Compare: https://github.com/llvm/llvm-project/compare/31ec0a684529...8ead003d8948
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