[all-commits] [llvm/llvm-project] bface3: [RISCV] Make SCS prologue interrupt safe on RISC-V

[Paul Kirth via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: bface3947ea15b45c78aff4792355651f72626a1
      https://github.com/llvm/llvm-project/commit/bface3947ea15b45c78aff4792355651f72626a1
  Author: Paul Kirth <paulkirth at google.com>
  Date:   2023-04-26 (Wed, 26 Apr 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
    M llvm/test/CodeGen/RISCV/shadowcallstack.ll

  Log Message:
  -----------
  [RISCV] Make SCS prologue interrupt safe on RISC-V

Prior to this patch the SCS prologue used the following instruction
sequence.

```
s[w|d]  ra, 0(gp)
addi    gp, gp, [4|8]
```

The problem with this sequence is that an interrupt occurring between the
store and the increment could clobber the value just written to the SCS.

https://reviews.llvm.org/D84414#inline-813203 pointed out a similar
issues that could have affected the epilogue.

This patch changes the instruction sequence in the prologue to:

```
addi    gp, gp, [4|8]
s[w|d]  ra, -[4|8](gp)
```

The downside to this is that there is now a data dependency between the
add and the store.

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D149099