[all-commits] [llvm/llvm-project] 124acb: [AMDGPU] Fix negative offset values interpretation...

[Janek van Oirschot via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 124acb7ca31aa358cc5f7b4a5d09edbd1c0cac84
      https://github.com/llvm/llvm-project/commit/124acb7ca31aa358cc5f7b4a5d09edbd1c0cac84
  Author: Janek van Oirschot <janek.vanoirschot at amd.com>
  Date:   2023-04-26 (Wed, 26 Apr 2023)

  Changed paths:
    M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
    M llvm/test/CodeGen/AMDGPU/si-triv-disjoint-mem-access.ll
    A llvm/test/CodeGen/AMDGPU/triv-disjoint-mem-access-neg-offset.mir

  Log Message:
  -----------
  [AMDGPU] Fix negative offset values interpretation in getMemOperandsWithOffset for DS

The offset values may result in an erroneous scheduling of a load before write for a memory location if the offset values are represented as negative values in MIR, despite actually being unsigned values. This representation in MIR happens as SelectionDAG::getConstant could go through APInt to represent the encoding which assumes the MSB of the encoding as a sign-bit, regardless of whether it is supposed to be a signed value. The 8-bit negative (interpreted) value gets cast to an unsigned 32 bit value in getMemOperandsWithOffset used for comparisons in areMemAccessesTriviallyDisjoint eventually leading to an erroneous schedule in the machine scheduler.

Reviewed By: arsenm, foad

Differential Revision: https://reviews.llvm.org/D149080