[all-commits] [llvm/llvm-project] 075202: [X86 isel] Fix permute mask calculation in lowerSh...

[Han Zhu via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 075202d126dfba6fd1503926808a2fcafab1714a
      https://github.com/llvm/llvm-project/commit/075202d126dfba6fd1503926808a2fcafab1714a
  Author: Han Zhu <zhuhan7737 at gmail.com>
  Date:   2023-04-24 (Mon, 24 Apr 2023)

  Changed paths:
    M llvm/lib/Target/X86/X86ISelLowering.cpp
    A llvm/test/CodeGen/X86/pr62242.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-5.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-5.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-7.ll

  Log Message:
  -----------
  [X86 isel] Fix permute mask calculation in lowerShuffleAsUNPCKAndPermute

This fixes [issue 62242](https://github.com/llvm/llvm-project/issues/62242)

This code block can potentially swap the order of V1 and V2 in Ops and therefore
also in the unpck instruction generated.
```
SDValue &Op = Ops[Elt & 1];
if (M < NumElts && (Op.isUndef() || Op == V1))
  Op = V1;
else if (NumElts <= M && (Op.isUndef() || Op == V2)) {
  Op = V2;
  NormM -= NumElts;
} else
  return SDValue();
```
But the permute mask is calculated assuming the first operand being V1 and
second V2, therefore causing a mis-compile.

First check if the input operands are swapped, and then calculate the permute
mask based on that.

Differential Revision: https://reviews.llvm.org/D148843