[all-commits] [llvm/llvm-project] 09b0f8: [RISCV] Let assembler accept vector memory operand...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 09b0f89c33f1b8babb0ca5ad1e65bad7d02645a5
      https://github.com/llvm/llvm-project/commit/09b0f89c33f1b8babb0ca5ad1e65bad7d02645a5
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-04-20 (Thu, 20 Apr 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoV.td
    M llvm/test/MC/RISCV/rvv/load.s
    M llvm/test/MC/RISCV/rvv/store.s
    M llvm/test/MC/RISCV/rvv/zvlsseg.s

  Log Message:
  -----------
  [RISCV] Let assembler accept vector memory operands that have an explicit 0 offset.

Binutils allows vector instructions with memory operands that
have an explicit 0 offset like 'vle8.v v0, 0(a0)'.

We already have support for this in the parser because the same
thing is allowed for atomics.

This patch changes the AsmOperand and AsmString for the vector
memory instructions to allow this.

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D148733