[all-commits] [llvm/llvm-project] 3e76d0: [AArch64][CodeGen] Allow vectors larger than hardw...

[Dinar Temirbulatov via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 3e76d012d174a2e33564a6d8476c7f88c7d1b4b8
      https://github.com/llvm/llvm-project/commit/3e76d012d174a2e33564a6d8476c7f88c7d1b4b8
  Author: Dinar Temirbulatov <dinar.temirbulatov at arm.com>
  Date:   2023-04-19 (Wed, 19 Apr 2023)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/test/CodeGen/AArch64/sve-fixed-length-ext-loads.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ext-loads.ll

  Log Message:
  -----------
  [AArch64][CodeGen] Allow vectors larger than hardware support to use SVE's load zero/sign-extend for fixed vectors.

Prefer to fold LOAD + SIGN/ZEROEXTEND to SVE load and sign extend instructions
for fixed-length-vectors even if a type is not representable on a hardware.

Differential Revision: https://reviews.llvm.org/D147533