[all-commits] [llvm/llvm-project] efd64c: [LLDB][RISCV] Add RVV register infos

[Emmmer via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: efd64c2f2506df3e2ed6d9da68e49f03fc31763c
      https://github.com/llvm/llvm-project/commit/efd64c2f2506df3e2ed6d9da68e49f03fc31763c
  Author: Emmmer <yjhdandan at 163.com>
  Date:   2023-04-19 (Wed, 19 Apr 2023)

  Changed paths:
    M lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_riscv64.h
    M lldb/source/Plugins/Process/Utility/RegisterInfos_riscv64.h

  Log Message:
  -----------
  [LLDB][RISCV] Add RVV register infos

RVV stands for "RISC-V V Extension", which adds 32 vector registers, and seven unprivileged CSRs (vstart, vxsat, vxrm, vcsr, vtype, vl, vlenb) to a base scalar RISC-V ISA.

The base vector extension is intended to provide general support for data-parallel execution within the 32-bit instruction encoding space, with later vector extensions supporting richer functionality for certain domains.

This patch adds the definitions of RVV registers in `RegisterInfos_riscv64.h`, whose purpose is to provide support (such as reading, writing, and calculating the offsets) for future register-related functions.

Reviewed By: kito-cheng

Differential Revision: https://reviews.llvm.org/D143374