[all-commits] [llvm/llvm-project] 0571ba: [clang-format] Handle Verilog assertions and loops

[eywdck2l via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 0571ba8d1b4dbe72e0856f9b84146cc6e152a4d0
      https://github.com/llvm/llvm-project/commit/0571ba8d1b4dbe72e0856f9b84146cc6e152a4d0
  Author: sstwcw <f0gukp2nk at protonmail.com>
  Date:   2023-04-16 (Sun, 16 Apr 2023)

  Changed paths:
    M clang/lib/Format/TokenAnnotator.cpp
    M clang/lib/Format/UnwrappedLineParser.cpp
    M clang/lib/Format/UnwrappedLineParser.h
    M clang/unittests/Format/FormatTestVerilog.cpp
    M clang/unittests/Format/TokenAnnotatorTest.cpp

  Log Message:
  -----------
  [clang-format] Handle Verilog assertions and loops

Assert statements in Verilog can optionally have an else part.  We
handle them like for `if` statements, except that an `if` statement in
the else part of an `assert` statement doesn't get merged with the
`else` keyword.  Like this:

    assert (x)
      $info();
    else
      if (y)
        $info();
      else if (z)
        $info();
      else
        $info();

`foreach` and `repeat` are now handled like for or while loops.

We used the type `TT_ConditionLParen` to mark the condition part so
they are handled in the same way as the condition part of an `if`
statement.  When the code being formatted is not in Verilog, it is
only set for `if` statements, not loops.  It's because loop conditions
are currently handled slightly differently, and existing behavior is
not supposed to change.  We formatted all files ending in `.cpp` and
`.h` in the repository with and without this change.  It showed that
setting the type for `if` statements doesn't change existing behavior.

And we noticed that we forgot to make the program print the list of
tokens when the number is not correct in `TokenAnnotatorTest`.  It's
fixed now.

Reviewed By: HazardyKnusperkeks

Differential Revision: https://reviews.llvm.org/D147895