[all-commits] [llvm/llvm-project] 8a21df: [mlir][openacc] Accept acc.serial has parent of ac...

[Valentin Clement (バレンタイン クレメン) via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 8a21dfe1bd9fa18651676062dfe17feb71fe2344
      https://github.com/llvm/llvm-project/commit/8a21dfe1bd9fa18651676062dfe17feb71fe2344
  Author: Valentin Clement <clementval at gmail.com>
  Date:   2023-04-13 (Thu, 13 Apr 2023)

  Changed paths:
    M mlir/include/mlir/Dialect/OpenACC/OpenACCOps.td
    M mlir/test/Dialect/OpenACC/ops.mlir

  Log Message:
  -----------
  [mlir][openacc] Accept acc.serial has parent of acc.yield op

acc.serial op is modeled on the acc.parallel op.
acc.yield operation must then accept acc.serial has a parent
operation.

Reviewed By: PeteSteinfeld, razvanlupusoru

Differential Revision: https://reviews.llvm.org/D148258