[all-commits] [llvm/llvm-project] 41eba6: [AArch64][GISel] Legalize non-power-of-two G_CTTZ

[Sam Elliott via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 41eba6cddec05fa41720ccf1eb5dd7a906050af0
      https://github.com/llvm/llvm-project/commit/41eba6cddec05fa41720ccf1eb5dd7a906050af0
  Author: Archibald Elliott <archibald.elliott at arm.com>
  Date:   2023-04-13 (Thu, 13 Apr 2023)

  Changed paths:
    M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-cttz-zero-undef.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-cttz.mir

  Log Message:
  -----------
  [AArch64][GISel] Legalize non-power-of-two G_CTTZ

The main change here is to add a `widenScalarToNextPow2` before the
`clampScalar` so that non-power-of-two sizes between 32 and 64 are
turned into s64 count trailing zeroes.

However, if you make the legalisation rules depend on TypeIdx 0 (the
output), then you still get crashes for the s65 testcase, which I solved
by instead flipping the rules around to be about TypeIdx 1 (the input),
with a `scalarSameSizeAs` at the end to tie index 0 to index 1. This,
incidentally, is how things are written for `G_CTLZ`.

Differential Revision: https://reviews.llvm.org/D147602