[all-commits] [llvm/llvm-project] aa1d26: [CodeGen][RISCV] Change Shadow Call Stack Register...

[Paul Kirth via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: aa1d2693c25622ea4a8ee2b622ba2a617e18ef88
      https://github.com/llvm/llvm-project/commit/aa1d2693c25622ea4a8ee2b622ba2a617e18ef88
  Author: Paul Kirth <paulkirth at google.com>
  Date:   2023-04-12 (Wed, 12 Apr 2023)

  Changed paths:
    M clang/docs/ShadowCallStack.rst
    M clang/lib/Driver/SanitizerArgs.cpp
    M clang/test/Driver/sanitizer-ld.c
    M compiler-rt/test/shadowcallstack/lit.cfg.py
    M llvm/docs/ReleaseNotes.rst
    M llvm/include/llvm/TargetParser/RISCVTargetParser.h
    M llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
    M llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
    M llvm/lib/Target/RISCV/RISCVSubtarget.cpp
    M llvm/lib/TargetParser/RISCVTargetParser.cpp
    M llvm/test/CodeGen/RISCV/reserved-regs.ll
    A llvm/test/CodeGen/RISCV/saverestore-scs.ll
    M llvm/test/CodeGen/RISCV/shadowcallstack.ll

  Log Message:
  -----------
  [CodeGen][RISCV] Change Shadow Call Stack Register to X3

ShadowCallStack implementation uses s2 register on RISC-V, but that
choice is problematic for reasons described in:

https://lists.riscv.org/g/sig-toolchains/message/544,
https://github.com/riscv-non-isa/riscv-elf-psabi-doc/issues/370, and
https://github.com/google/android-riscv64/issues/72

The concern over the register choice was also brought up in
https://reviews.llvm.org/D84414.

https://reviews.llvm.org/D84414#2228666 said:

```
  "If the register choice is the only concern about this work, then I think
  we can probably land it as-is and fixup the register choice if we see
  major drawbacks later. Yes, it's an ABI issue, but on the other hand the
  shadow call stack is not a standard ABI anyway.""
```

Since we have now found a sufficient reason to fixup the register
choice, we should go ahead and update the implementation. We propose
using x3(gp) which is now the platform register in the RISC-V ABI.

Reviewed By: asb, hiraditya, mcgrathr, craig.topper

Differential Revision: https://reviews.llvm.org/D146463