[all-commits] [llvm/llvm-project] 9af924: [AArch64][SVE] Extend predicated fadd/fsub pattern...

[David Green via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 9af92455f36f08c111625dcd4951f91003bacee2
      https://github.com/llvm/llvm-project/commit/9af92455f36f08c111625dcd4951f91003bacee2
  Author: David Green <david.green at arm.com>
  Date:   2023-04-12 (Wed, 12 Apr 2023)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
    M llvm/test/CodeGen/AArch64/sve-fp-combine.ll

  Log Message:
  -----------
  [AArch64][SVE] Extend predicated fadd/fsub patterns to negative zero

This adds -0.0 patterns for fadd and fsub, to go with D147723. The fsub pattern
is only added for completeness but with -0.0 being the neutral element the fadd
case comes up from vectorized reductions.

Differential Revision: https://reviews.llvm.org/D147724