[all-commits] [llvm/llvm-project] f86a5f: [NFC][AArch64] Regenerate G_CTLZ Legalizer Test

[Sam Elliott via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: f86a5ff7062a14f63cf98c6f3a405444bd896d04
      https://github.com/llvm/llvm-project/commit/f86a5ff7062a14f63cf98c6f3a405444bd896d04
  Author: Archibald Elliott <archibald.elliott at arm.com>
  Date:   2023-04-12 (Wed, 12 Apr 2023)

  Changed paths:
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-ctlz.mir

  Log Message:
  -----------
  [NFC][AArch64] Regenerate G_CTLZ Legalizer Test

Differential Revision: https://reviews.llvm.org/D147515


  Commit: 56065f8f02ea01363f98011a4d6aa568d8b10d4f
      https://github.com/llvm/llvm-project/commit/56065f8f02ea01363f98011a4d6aa568d8b10d4f
  Author: Archibald Elliott <archibald.elliott at arm.com>
  Date:   2023-04-12 (Wed, 12 Apr 2023)

  Changed paths:
    M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-ctlz.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir

  Log Message:
  -----------
  [AArch64][GISel] Legalize non-power-of-two G_CTLZ

This fixes a crash found in PR61549, and adds test coverage for other
sizes that cannot be selected.

Differential Revision: https://reviews.llvm.org/D147516


  Commit: b3a4dbfd8a338e2a790ea27fefd34faeee3a7ada
      https://github.com/llvm/llvm-project/commit/b3a4dbfd8a338e2a790ea27fefd34faeee3a7ada
  Author: Archibald Elliott <archibald.elliott at arm.com>
  Date:   2023-04-12 (Wed, 12 Apr 2023)

  Changed paths:
    A llvm/test/CodeGen/AArch64/pr61549.ll

  Log Message:
  -----------
  [NFC][AArch64] Add Test for PR61549

Differential Revision: https://reviews.llvm.org/D147517


  Commit: 17cd511007fd86cf2a4c5a6e20e1845eb5af3eb8
      https://github.com/llvm/llvm-project/commit/17cd511007fd86cf2a4c5a6e20e1845eb5af3eb8
  Author: Archibald Elliott <archibald.elliott at arm.com>
  Date:   2023-04-12 (Wed, 12 Apr 2023)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    M llvm/test/CodeGen/AArch64/pr61549.ll

  Log Message:
  -----------
  [DAGCombiner] Fix (shl (ctlz x) n) for non-power-of-two Data

This DAGCombine is not valid for some combinations of the known bits
of x and non-power-of-two widths of x. As shown in the bug:
- The bitwidth of x is 35 (n=5)
- The unknown bits of x is only the least significant bit
- This gives the result of the ctlz two possible values: 34 or 35, both
  of which will give 1 when left-shifted 5 bits.
- So the `eor x, 1` that this optimisation would give is not correct.

A similar instcombine optimisation is only applied when the width of x is
a power-of-two. GlobalISel does not have this bug, as shown by the testcase.

Fixes #61549

Differential Revision: https://reviews.llvm.org/D147518


Compare: https://github.com/llvm/llvm-project/compare/63a8ca3fe97d...17cd511007fd