[all-commits] [llvm/llvm-project] 64d29e: [RISCV] Add segment load/store to getTgtMemIntrinsic.
Craig Topper via All-commits
all-commits at lists.llvm.org
Tue Apr 11 11:32:51 PDT 2023
Branch: refs/heads/main
Home: https://github.com/llvm/llvm-project
Commit: 64d29e8ecb888c9249f268453d90ba5a54341cd7
https://github.com/llvm/llvm-project/commit/64d29e8ecb888c9249f268453d90ba5a54341cd7
Author: Craig Topper <craig.topper at sifive.com>
Date: 2023-04-11 (Tue, 11 Apr 2023)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
Log Message:
-----------
[RISCV] Add segment load/store to getTgtMemIntrinsic.
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