[all-commits] [llvm/llvm-project] 64d29e: [RISCV] Add segment load/store to getTgtMemIntrinsic.

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 64d29e8ecb888c9249f268453d90ba5a54341cd7
      https://github.com/llvm/llvm-project/commit/64d29e8ecb888c9249f268453d90ba5a54341cd7
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-04-11 (Tue, 11 Apr 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp

  Log Message:
  -----------
  [RISCV] Add segment load/store to getTgtMemIntrinsic.