[all-commits] [llvm/llvm-project] 3bc1e0: AMDGPU: Created a subclass for the return address ...

[Changpeng Fang via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 3bc1e084eef09dcc7e5b77f70e904b2edb27791c
      https://github.com/llvm/llvm-project/commit/3bc1e084eef09dcc7e5b77f70e904b2edb27791c
  Author: Changpeng Fang <changpeng.fang at amd.com>
  Date:   2023-04-10 (Mon, 10 Apr 2023)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
    M llvm/lib/Target/AMDGPU/SIInstructions.td
    M llvm/lib/Target/AMDGPU/SIRegisterInfo.td
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-assert-align.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-sibling-call.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-tail-call.ll
    M llvm/test/CodeGen/AMDGPU/inline-asm.i128.ll
    M llvm/test/CodeGen/AMDGPU/partial-regcopy-and-spill-missed-at-regalloc.ll

  Log Message:
  -----------
  AMDGPU: Created a subclass for the return address operand in the tail call return instruction

Summary:
  This is to avoid using the callee saved registers for the return address
of the tail call return instruction.

Reviewers:
  arsenm, cdevadas

Differential Revision:
  https://reviews.llvm.org/D147096