[all-commits] [llvm/llvm-project] 0ab155: [TableGen] Reorder some checks in TreePatternNode:...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 0ab1559a3d92aad896aebaf7912ee6789d6bef06
      https://github.com/llvm/llvm-project/commit/0ab1559a3d92aad896aebaf7912ee6789d6bef06
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-04-09 (Sun, 09 Apr 2023)

  Changed paths:
    M llvm/utils/TableGen/CodeGenDAGPatterns.cpp

  Log Message:
  -----------
  [TableGen] Reorder some checks in TreePatternNode::isIsomorphicTo to speedup -gen-dag-isel for RISC-V.

Comparing types is quite expensive when hardware modes are being
used. Checking the operator first can let us detect mismatches
earlier without checking types.