[all-commits] [llvm/llvm-project] b6ea46: [RISCV] Add DAG combine to fold (sub 0, (setcc x, ...

[Liao Chunyu via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: b6ea46fe72c2ee192b334be6fffaae35a10f5900
      https://github.com/llvm/llvm-project/commit/b6ea46fe72c2ee192b334be6fffaae35a10f5900
  Author: LiaoChunyu <chunyu at iscas.ac.cn>
  Date:   2023-04-07 (Fri, 07 Apr 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/alu64.ll
    M llvm/test/CodeGen/RISCV/bittest.ll
    M llvm/test/CodeGen/RISCV/fpclamptosat.ll
    M llvm/test/CodeGen/RISCV/rotl-rotr.ll
    M llvm/test/CodeGen/RISCV/rvv/fpclamptosat_vec.ll
    M llvm/test/CodeGen/RISCV/shift-amount-mod.ll
    M llvm/test/CodeGen/RISCV/shift-masked-shamt.ll
    M llvm/test/CodeGen/RISCV/shifts.ll
    M llvm/test/CodeGen/RISCV/wide-scalar-shift-by-byte-multiple-legalization.ll
    M llvm/test/CodeGen/RISCV/wide-scalar-shift-legalization.ll

  Log Message:
  -----------
  [RISCV] Add DAG combine to fold (sub 0, (setcc x, 0, setlt)) -> (sra x , xlen - 1)

The result of sub + setcc is 0 or 1 for all bits.
The sra instruction get the same result.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D147538