[all-commits] [llvm/llvm-project] 846712: [DAG] combineSelect - select(i1, vXi1, vXi1) - only ...

[Simon Pilgrim via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 846712b0cb133f0ebfaf5be41818183b4c86f0a1
      https://github.com/llvm/llvm-project/commit/846712b0cb133f0ebfaf5be41818183b4c86f0a1
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2023-04-06 (Thu, 06 Apr 2023)

  Changed paths:
    M llvm/lib/Target/X86/X86ISelLowering.cpp
    A llvm/test/CodeGen/X86/pr61524.ll

  Log Message:
  -----------
  [DAG] combineSelect - select(i1,vXi1,vXi1) - only cast <X x i1> constants to iX pre-legalization or if its a legal type

Fixes #61524