[all-commits] [llvm/llvm-project] 5f2145: [RISCV] Use non-strided load if VL=1 for optimized...

[Luke Lau via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 5f2145adf9e343e950935cac1c9030f8ca597912
      https://github.com/llvm/llvm-project/commit/5f2145adf9e343e950935cac1c9030f8ca597912
  Author: Luke Lau <luke at igalia.com>
  Date:   2023-04-06 (Thu, 06 Apr 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll

  Log Message:
  -----------
  [RISCV] Use non-strided load if VL=1 for optimized zero stride loads

When optimizing vmv.s.x/vmv.v.x's of scalar loads, if VL is known to be
1 then we don't need to perform a stride of x0, and can just do a
regular load.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D147609