[all-commits] [llvm/llvm-project] 2c5786: [RISCV] Add vector load/store intrinsics to getTgt...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 2c57868e2e877f73c339796c3374ae660bb77f0d
      https://github.com/llvm/llvm-project/commit/2c57868e2e877f73c339796c3374ae660bb77f0d
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-04-05 (Wed, 05 Apr 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/early-clobber-tied-def-subreg-liveness.ll
    M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll

  Log Message:
  -----------
  [RISCV] Add vector load/store intrinsics to getTgtMemIntrinsic.

This constructs a proper memory operand for these intrinsics.

Segment load/store will be added in a separate patch.

Reviewed By: kito-cheng

Differential Revision: https://reviews.llvm.org/D147119