[all-commits] [llvm/llvm-project] 4f66ca: [AArch64][SME] Disable ZA LDR/STR addressing optim...

[david-arm via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 4f66ca3fb7d5a1cdc9d597604b58e230ad6ba0dc
      https://github.com/llvm/llvm-project/commit/4f66ca3fb7d5a1cdc9d597604b58e230ad6ba0dc
  Author: David Sherwood <david.sherwood at arm.com>
  Date:   2023-04-05 (Wed, 05 Apr 2023)

  Changed paths:
    M llvm/lib/Target/AArch64/SMEInstrFormats.td
    M llvm/test/CodeGen/AArch64/sme-intrinsics-loads.ll
    M llvm/test/CodeGen/AArch64/sme-intrinsics-stores.ll

  Log Message:
  -----------
  [AArch64][SME] Disable ZA LDR/STR addressing optimisations

Since the same encoded offset is used for both the vector
select offset and the address offset we have to spot two
patterns simulatenously in the ldr/str intrinsic inputs, i.e.

vector select = base + off
address = base + (off * VL)

whereas currently we only look for the address pattern. I
don't think this is possible in tablegen, so I suspect we'll
have to do this manually as part of lowering or as a target
DAG combine. For now, I've removed these tablegen patterns
so that we at least do the correct thing even if the code
quality isn't great.

I've also changed some of the ldr/str tests to pass in the
same vector select pattern (base + off) as the address
pattern.

Differential Revision: https://reviews.llvm.org/D147433