[all-commits] [llvm/llvm-project] 8f5db5: [AArch64][GlobalISel] Add support for some across-...

[Vladislav Dzhidzhoev via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 8f5db5332b2a4e9465f12e3192120eb28935e1a0
      https://github.com/llvm/llvm-project/commit/8f5db5332b2a4e9465f12e3192120eb28935e1a0
  Author: Vladislav Dzhidzhoev <vdzhidzhoev at accesssoftek.com>
  Date:   2023-04-05 (Wed, 05 Apr 2023)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64InstrGISel.td
    M llvm/lib/Target/AArch64/AArch64InstrInfo.td
    M llvm/lib/Target/AArch64/AArch64RegisterInfo.td
    M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
    M llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
    M llvm/test/CodeGen/AArch64/aarch64-addv.ll
    M llvm/test/CodeGen/AArch64/arm64-fminv.ll
    M llvm/test/CodeGen/AArch64/arm64-neon-across.ll
    M llvm/test/CodeGen/AArch64/arm64-neon-add-pairwise.ll

  Log Message:
  -----------
  [AArch64][GlobalISel] Add support for some across-vector NEON intrinsics

Support uaddv, saddv, umaxv, smaxv, uminv, sminv, fmaxv, fminv,
fmaxnmv, fminnmv intrinsics in GlobalISel.

GlobalISelEmitter couldn't import SelectionDAG patterns containing nodes
with 8-bit result type, since they had untyped values. Therefore,
register type for FPR8 is set to i8 to eliminate untyped nodes in these
patterns.

Differential Revision: https://reviews.llvm.org/D146531