[all-commits] [llvm/llvm-project] 7f05bd: [AArch64][SME] Fix an infinite loop in DAGCombine ...

[Dinar Temirbulatov via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 7f05bdf4ee1c4a6779ecde1e44a889c4cef72269
      https://github.com/llvm/llvm-project/commit/7f05bdf4ee1c4a6779ecde1e44a889c4cef72269
  Author: Dinar Temirbulatov <dinar.temirbulatov at arm.com>
  Date:   2023-04-05 (Wed, 05 Apr 2023)

  Changed paths:
    M llvm/include/llvm/CodeGen/TargetLowering.h
    M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/lib/Target/AArch64/AArch64ISelLowering.h
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.h
    M llvm/lib/Target/X86/X86ISelLowering.cpp
    M llvm/lib/Target/X86/X86ISelLowering.h
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-extends.ll

  Log Message:
  -----------
  [AArch64][SME] Fix an infinite loop in DAGCombine related to adding -force-streaming-compatible-sve flag.

Compiler hits infinite loop in DAGCombine. For force-streaming-compatible-sve
mode we have custom lowering for 128-bit vector splats and later in
DAGCombiner::SimplifyVCastOp() we scalarized SPLAT because we have custom
lowering for SME. Later, we restored SPLAT opertion via performMulCombine().