[all-commits] [llvm/llvm-project] 6a8d8f: [AArch64][DAGCombiner]: combine <2xi64> add/sub.

[hassnaaHamdi via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 6a8d8f3e28aed1b77356be74ee5109d7bdd37dd1
      https://github.com/llvm/llvm-project/commit/6a8d8f3e28aed1b77356be74ee5109d7bdd37dd1
  Author: Hassnaa Hamdi <hassnaa.hamdi at arm.com>
  Date:   2023-04-05 (Wed, 05 Apr 2023)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    A llvm/test/CodeGen/AArch64/aarch64-combine-add-sub-mul.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-int-rem.ll

  Log Message:
  -----------
  [AArch64][DAGCombiner]: combine <2xi64> add/sub.

64-bit vector mul is not supported in NEON,
so we use the SVE's mul.
To improve the performance, we can go one step further,
and use SVE's add/sub, so that we can use SVE's mla/mls.
That works on these patterns:
// This works on the patterns of:
//   add v1, (mul v2, v3)
//   sub v1, (mul v2, v3)

Reviewed By: david-arm

Differential Revision: https://reviews.llvm.org/D147236