[all-commits] [llvm/llvm-project] 74cc43: [clang-format] Add option for having one port per ...

[eywdck2l via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 74cc4389f37d753bf07f1b4a4a4c5e09433d9231
      https://github.com/llvm/llvm-project/commit/74cc4389f37d753bf07f1b4a4a4c5e09433d9231
  Author: sstwcw <f0gukp2nk at protonmail.com>
  Date:   2023-04-04 (Tue, 04 Apr 2023)

  Changed paths:
    M clang/docs/ClangFormatStyleOptions.rst
    M clang/include/clang/Format/Format.h
    M clang/lib/Format/Format.cpp
    M clang/lib/Format/FormatToken.h
    M clang/lib/Format/TokenAnnotator.cpp
    M clang/unittests/Format/ConfigParseTest.cpp
    M clang/unittests/Format/FormatTestVerilog.cpp
    M clang/unittests/Format/TokenAnnotatorTest.cpp

  Log Message:
  -----------
  [clang-format] Add option for having one port per line in Verilog

We added the option `VerilogBreakBetweenInstancePorts` to put ports on
separate lines in module instantiations.  We made it default to true
because style guides mostly recommend it that way for example:

https://github.com/lowRISC/style-guides/blob/master/VerilogCodingStyle.md#module-instantiation

Reviewed By: HazardyKnusperkeks

Differential Revision: https://reviews.llvm.org/D147327