[all-commits] [llvm/llvm-project] 971a45: [RISCV] Model vlseg/vsseg in interleaved memory ops

[Luke Lau via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 971a4501f7f2017816e3365f0008418fd978a9e7
      https://github.com/llvm/llvm-project/commit/971a4501f7f2017816e3365f0008418fd978a9e7
  Author: Luke Lau <luke at igalia.com>
  Date:   2023-04-04 (Tue, 04 Apr 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
    M llvm/test/Transforms/LoopVectorize/RISCV/interleaved-accesses.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/interleaved-cost.ll

  Log Message:
  -----------
  [RISCV] Model vlseg/vsseg in interleaved memory ops

If the legalized type is a legal interleaved access type (i.e. there's a
supported vlseg/vsseg instruction for it), the interleaved access pass
will pick any interleaved memory op (wide load + shuffles) and lower it
into a vlseg/vsseg intrinsic.

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D146522