[all-commits] [llvm/llvm-project] 932911: [AArch64] Remove redundant `mov 0` instruction for...

[JinGu Kang via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 932911d6b10a7503a0b9c5e1a2ddb581cc3421bf
      https://github.com/llvm/llvm-project/commit/932911d6b10a7503a0b9c5e1a2ddb581cc3421bf
  Author: Jingu Kang <jingu.kang at arm.com>
  Date:   2023-04-03 (Mon, 03 Apr 2023)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp
    M llvm/test/CodeGen/AArch64/aarch64-neon-vector-insert-uaddlv.ll
    A llvm/test/CodeGen/AArch64/implicitly-set-zero-high-64-bits.ll
    M llvm/test/CodeGen/AArch64/peephole-insvigpr.mir

  Log Message:
  -----------
  [AArch64] Remove redundant `mov 0` instruction for high 64-bits

If MI sets zero for high 64-bits implicitly, remove `mov 0` for high 64-bits.
For example,

 %1:fpr64 = nofpexcept FCVTNv4i16 %0:fpr128, implicit $fpcr
 %2:fpr64 = MOVID 0
 %4:fpr128 = IMPLICIT_DEF
 %3:fpr128 = INSERT_SUBREG %4:fpr128(tied-def 0), killed %2:fpr64, %subreg.dsub
 %6:fpr128 = IMPLICIT_DEF
 %5:fpr128 = INSERT_SUBREG %6:fpr128(tied-def 0), killed %1:fpr64, %subreg.dsub
 %7:fpr128 = INSvi64lane %5:fpr128(tied-def 0), 1, killed %3:fpr128, 0
 ==>
 %1:fpr64 = nofpexcept FCVTNv4i16 %0:fpr128, implicit $fpcr
 %6:fpr128 = IMPLICIT_DEF
 %7:fpr128 = INSERT_SUBREG %6:fpr128(tied-def 0), killed %1:fpr64, %subreg.dsub

Differential Revision: https://reviews.llvm.org/D147235