[all-commits] [llvm/llvm-project] ec26c9: [RISCV] Lower fixed length interleaved accesses vi...

[Luke Lau via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: ec26c9cdc002bdbf247eac0b2563f44f5e90e840
      https://github.com/llvm/llvm-project/commit/ec26c9cdc002bdbf247eac0b2563f44f5e90e840
  Author: Luke Lau <luke at igalia.com>
  Date:   2023-04-02 (Sun, 02 Apr 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.h
    M llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
    M llvm/test/CodeGen/RISCV/O3-pipeline.ll
    A llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access-zve32x.ll
    A llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shufflevector-vnsrl.ll
    A llvm/test/Transforms/InterleavedAccess/RISCV/interleaved-accesses.ll
    A llvm/test/Transforms/InterleavedAccess/RISCV/lit.local.cfg
    A llvm/test/Transforms/InterleavedAccess/RISCV/zve32x.ll
    A llvm/test/Transforms/InterleavedAccess/RISCV/zvl32b.ll

  Log Message:
  -----------
  [RISCV] Lower fixed length interleaved accesses via vssegN/vlsegN

This enables the interleaved access pass on O1 and above, and causes
interleaving/deinterleaving shuffles of fixed length vectors with
stores/loads to be lowered into vssegN/vlsegN.

We need to be careful and make sure that we only lower vsseg/vlseg
whenever we know the fixed vector type will fit within the minimum vlen,
and that the interleaving factor is supported for the given LMUL.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D145085