[all-commits] [llvm/llvm-project] 80f3be: Revert "[RISCV] Lower fixed length interleaved acc...

[Luke Lau via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 80f3be960355081935d21d6388c1442672a3c45f
      https://github.com/llvm/llvm-project/commit/80f3be960355081935d21d6388c1442672a3c45f
  Author: Luke Lau <luke at igalia.com>
  Date:   2023-04-02 (Sun, 02 Apr 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.h
    M llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
    M llvm/test/CodeGen/RISCV/O3-pipeline.ll
    R llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access-zve32x.ll
    R llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shufflevector-vnsrl.ll
    R llvm/test/Transforms/InterleavedAccess/RISCV/interleaved-accesses.ll
    R llvm/test/Transforms/InterleavedAccess/RISCV/zve32x.ll
    R llvm/test/Transforms/InterleavedAccess/RISCV/zvl32b.ll

  Log Message:
  -----------
  Revert "[RISCV] Lower fixed length interleaved accesses via vssegN/vlsegN"

This reverts commit b95913e8c3a3521b85d689a358e620d89a4e83de.