[all-commits] [llvm/llvm-project] 6217f4: [RISCV] Lower inline asm m with offset to register...

Mikhail R. Gadelha via All-commits all-commits at lists.llvm.org
Fri Mar 31 09:25:06 PDT 2023

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 6217f472a6357426ebba531c5cc24887e59d3285
  Author: Mikhail R. Gadelha <mikhail at igalia.com>
  Date:   2023-03-31 (Fri, 31 Mar 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/test/CodeGen/RISCV/inline-asm.ll

  Log Message:
  [RISCV] Lower inline asm m with offset to register+imm.

As part of D145584, we noticed that llvm was generating suboptimal code
for constraint m when the operand can be be lowered to reg+imm form: it
was being selected as a single register rather than register+imm. This
caused an unnecessary 'addi' to be gen for each m constraint.

This patch changes llvm to select register+imm. This might generate code
that cannot be assembled, but matches gcc's behavior.

Reviewed By: craig.topper, kito-cheng

Differential Revision: https://reviews.llvm.org/D146245

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