[all-commits] [llvm/llvm-project] 5b0705: [RISCV] Slightly weaken expanded seq_cst atomic op...

[Alex Bradbury via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 5b0705961841349c3b90a46e5349cd9469e0382f
      https://github.com/llvm/llvm-project/commit/5b0705961841349c3b90a46e5349cd9469e0382f
  Author: Alex Bradbury <asb at igalia.com>
  Date:   2023-03-30 (Thu, 30 Mar 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVExpandAtomicPseudoInsts.cpp
    M llvm/test/CodeGen/RISCV/atomic-cmpxchg-branch-on-result.ll
    M llvm/test/CodeGen/RISCV/atomic-cmpxchg-flag.ll
    M llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll
    M llvm/test/CodeGen/RISCV/atomic-rmw.ll
    M llvm/test/CodeGen/RISCV/atomicrmw-uinc-udec-wrap.ll

  Log Message:
  -----------
  [RISCV] Slightly weaken expanded seq_cst atomic op to match reference mapping in in the spec

Table A.6 in the RISC-V ISA Manual indicates that sequentially
consistent atomic ops that have a matching instruction should be mapped
to `amo<op>.{w|d}.aqrl`. But sequentially consistent operations that are
mapped to lr/sc should produce `loop: lr.{w|d}.aqrl; <op>; sc.{w|d}.rl;
bnez loop`. Previously, LLVM produced an `sc.{w|d}.aqrl` which was
stronger than necessary. This patch adjusts the relevant logic so that a
`sc.{w|d}.rl` is produced.

Differential Revision: https://reviews.llvm.org/D146933