[all-commits] [llvm/llvm-project] 51d48a: [flang] Reimplement C1406 check as a warning

[Peter Klausler via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 51d48a3e6609c17299a16e8e823af6901be23c11
      https://github.com/llvm/llvm-project/commit/51d48a3e6609c17299a16e8e823af6901be23c11
  Author: Peter Klausler <pklausler at nvidia.com>
  Date:   2023-03-27 (Mon, 27 Mar 2023)

  Changed paths:
    M flang/docs/Extensions.md
    M flang/lib/Semantics/resolve-names.cpp
    M flang/test/Semantics/modfile43.f90

  Log Message:
  -----------
  [flang] Reimplement C1406 check as a warning

Constraint C1406 in Fortran 2018 prohibits the USE of the same module
name as both an intrinsic module and a non-intrinsic module in a scope.
The current check misinterprets the constraint as applying only to
explicitly INTRINSIC or NON_INTRINSIC module natures.

Change the check to also apply to non-explicit module natures, and
also downgrade it to a portability warning, since there is no ambiguity
and I suspect that we need to accept this usage when building f18's
own intrinsic modules.

Differential Revision: https://reviews.llvm.org/D146576