[all-commits] [llvm/llvm-project] 612635: [PowerPC] Implement 64-bit ELFv2 Calling Conventio...

[Amy Kwan via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 6126356d829be32e2195b8ddf8b908ab417ff7f5
      https://github.com/llvm/llvm-project/commit/6126356d829be32e2195b8ddf8b908ab417ff7f5
  Author: Amy Kwan <amy.kwan1 at ibm.com>
  Date:   2023-03-27 (Mon, 27 Mar 2023)

  Changed paths:
    M llvm/lib/Target/PowerPC/PPCCallingConv.cpp
    M llvm/lib/Target/PowerPC/PPCCallingConv.h
    M llvm/lib/Target/PowerPC/PPCCallingConv.td
    M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
    A llvm/test/CodeGen/PowerPC/GlobalISel/irtranslator-args-lowering-fp128.ll
    A llvm/test/CodeGen/PowerPC/GlobalISel/irtranslator-args-lowering-mixed-types.ll
    A llvm/test/CodeGen/PowerPC/GlobalISel/irtranslator-args-lowering-scalar.ll
    A llvm/test/CodeGen/PowerPC/GlobalISel/irtranslator-args-lowering-vectors.ll
    M llvm/test/CodeGen/PowerPC/GlobalISel/irtranslator-args-lowering.ll

  Log Message:
  -----------
  [PowerPC] Implement 64-bit ELFv2 Calling Convention in TableGen (for integers/floats/vectors in registers)

This patch partially implements the parameter passing rules outlined in the
ELFv2 ABI within TableGen. Specifically, it implements the parameter assignment
of integers, floats, and vectors within registers - where the GPR numbering will
be "skipped" depending on the ordering of floats and vectors that appear within
a parameter list.

As we begin to adopt GlobalISel to the PowerPC backend, there is a need for a
TableGen definition that encapsulates the ELFv2 parameter passing rules. Thus,
this patch also changes the default calling convention that is returned within
the ccAssignFnForCall() function used in our GlobalISel implementation, and also
adds some additional testing of the calling convention that is implemented.

Future patches that build on top of this initial TableGen definition will aim to
add more of the ABI complexities, including support for additional types and
also in-memory arguments.

Differential Revision: https://reviews.llvm.org/D137504


  Commit: 3508f123353c0a145ee79cebb972f46fcb97bf1e
      https://github.com/llvm/llvm-project/commit/3508f123353c0a145ee79cebb972f46fcb97bf1e
  Author: Amy Kwan <amy.kwan1 at ibm.com>
  Date:   2023-03-27 (Mon, 27 Mar 2023)

  Changed paths:
    M llvm/lib/Target/PowerPC/GISel/PPCInstructionSelector.cpp
    M llvm/lib/Target/PowerPC/GISel/PPCLegalizerInfo.cpp
    M llvm/lib/Target/PowerPC/GISel/PPCRegisterBankInfo.cpp
    M llvm/lib/Target/PowerPC/GISel/PPCRegisterBankInfo.h
    M llvm/lib/Target/PowerPC/GISel/PPCRegisterBanks.td
    M llvm/lib/Target/PowerPC/PPCGenRegisterBankInfo.def
    M llvm/test/CodeGen/PowerPC/GlobalISel/float-arithmetic.ll
    A llvm/test/CodeGen/PowerPC/GlobalISel/ppc-isel-arithmentic-vec.ll
    A llvm/test/CodeGen/PowerPC/GlobalISel/ppc-isel-logical-vec.ll
    A llvm/test/CodeGen/PowerPC/GlobalISel/ppc-isel-ret-and-bitcast-vec.ll

  Log Message:
  -----------
  [PowerPC][GISel] Add initial GlobalISel support for vector functions.

This patch adds the initial support for vector functions and register banks
within GlobalISel. With this patch, we are able to support simple functions that
return vectors, and also functions that perform simple operations.

This patch also:
- Legalizes vector types for G_AND, G_OR, G_XOR, G_ADD, G_SUB, G_BITCAST, G_FADD, G_FSUB
- Introduce initial support for bitcasting (that will need to be extended upon)
- Add various different test cases to for test vector support within GlobalISel

Differential Revision: https://reviews.llvm.org/D137785


Compare: https://github.com/llvm/llvm-project/compare/03df67e7858e...3508f123353c