[all-commits] [llvm/llvm-project] 6cef32: [clang-format] Don't squash Verilog escaped identi...

[eywdck2l via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 6cef325481a8efc039ae9df5630609fd3a84560c
      https://github.com/llvm/llvm-project/commit/6cef325481a8efc039ae9df5630609fd3a84560c
  Author: sstwcw <f0gukp2nk at protonmail.com>
  Date:   2023-03-26 (Sun, 26 Mar 2023)

  Changed paths:
    M clang/lib/Format/TokenAnnotator.cpp
    M clang/unittests/Format/FormatTestBase.h
    M clang/unittests/Format/FormatTestVerilog.cpp

  Log Message:
  -----------
  [clang-format] Don't squash Verilog escaped identifiers

An escaped identifier always needs a space following it so the parser
can tell it apart from the next token.

The unit tests are changed to use `FormatTestBase.h` because we need the
2-argument version of `verifyFormat`.  We also added the `messUp`
virtual function because Verilog needs a different version of it.

Reviewed By: HazardyKnusperkeks

Differential Revision: https://reviews.llvm.org/D146401